The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. In the course of integrated circuit evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs.
As semiconductor device sizes continue to shrink, new packaging technologies have been developed to accommodate (and to take advantage of) the small semiconductor device sizes. One type of packaging technology is wafer level packaging, where the IC devices are packaged at the wafer level, before the wafer is sliced. However, existing wafer level packaging techniques may be expensive and may not be fully compatible with current Complementary Metal-Oxide-Semiconductor (CMOS) fabrication processes.
Therefore, while existing wafer level packaging methods have been generally adequate for their intended purposes, they have not been entirely satisfactory in every aspect.